Digit storage circuit



Feb. 18, 1958 w, M, FURLOW, JR 2,824,222

DIGIT STORAGE CIRCUIT Filed Feb. 26, 1954 15;: IaKn GaKn INVENTORV` WILLIAM M. FURLOW JR.

BY 'm f ATTORNEYf United States arent 2,824,222 DIGrr sroRAGE CIRCUIT William M. Furlow, Jr., Arlington, Va., assignor to the United States of America as represented by the Secretary of the Navy ApplicationFebruary 26, 1954, Serial No. 412,965 3 Claims. (Cl. Z50- 27) (Granted under Title 35, U. S. Code (1952), sec. 266) This invention relates generally to unstable trigger circuits and more particularly to binary digit storage circuits.`

In the computer and analogous arts, it is often necessary to store a binary indication for a finite period of time while other information is read into the device or other storage time desired, the device is designed to reset itself` after a certain length of time. The device is also designed so that the pulse which reads out the condition of the circuit automatically resets the device to its stable state. It was also desired to provide a circuit which would recover quickly so that it would be responsive with-` in a short interval to succeeding pulses.

One object of this invention, therefore, is to provide an improved binary digit storage circuit.

Another object of this invention is to provide an improved storage circuit in which the read out signal resets the circuit to an initial condition. t

Another object of this invention is to provide an improved cathode coupled multivibrator which remains in an unstable state a relatively long time but which is re- Most of the circuits are varia-4 sponsive to additional pulses in relatively short periods.

Another object of this invention is to provide an improved binary storage circuit the output of which may be fed to a low impedance load.

Another object of the invention is to provide a novel binary storage circuit having separate read in and read out circuits.

Other objects and many of the attendant advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

Figure 1 represents a schematic drawing of a preferred embodiment of the invention.

Figure 2 represents a schematic drawing of another embodiment of the invention.

As shown in Figure 1, the circuit contains two tubes, the left one of which is normally conducting. When the left tube is conducting, the circuit is in the state which will be termed state 0. A negative pulse applied to the grid of the left tube will cause it to cutoff and the right tube to conduct; this state of conduction of the circuit will be termed state 1. The application of a read out signal, a negative pulse, to the plate of the left tube and the grid of the right tube causes the circuit to remain at or return to state 0 depending on the state of the circuit when it receives the read out signal. An output pulse is produced at the time ofread out if the right tube had been conducting and was cutoi, i. e., if the circuit was in state l at read out, an output pulse will be obtained.

In the circuit shown in Fig. 1, the triodes 11 and 12 may be halves of a dual tube such as a 6BN7 or its equivalent. The negative pulse representing a binary indication is` applied across input or read in terminals 13. The pulse is transmitted through coupling condenser 14 to the grid of tube 11. Until the application of this negative pulse, tube 11 is conducting by virtue of the voltage applied through resistance 15 to the plate of tube 11 and through resistance 16 to the grid of tube 11. The negative pulse applied to the grid of tube 11 drives the grid below cutoff. As a result of this cutoi the voltage rises on the plate `of tube 11, and the grid of tube 12, which is connected to the plate of tube 11 through condenser 17 becomes positive as condenser 17 is charged.

As the grid of tube 12 becomes more positive, it begins to conduct. The connection between B| and the plate of tube `12includes no voltage dropping element, therefore the current iiow through tube 12 and the cornmon cathode resistor 18 biases the cathode more positively than it did when tube 11 was conducting. Thus, after the negative read in pulse has been applied, the circuit is changed to asemi-stable state in which tube 12 isA conducting, i. e., state l. It will be explained below why state 1 is not a completely stable state.

After tube 11 has been cutoff by the negative read in pulse, condenser 14 begins to recharge through resistance 16 and immediately starts to raise the grid voltage of tube 11. In the absence of other circuit connections, the grid would be charged to a voltage above cutoi in a time determined by the time constant of resistance 16 and condenser 14. inasmuch as it is desired to store the binary information for some finite period which may be very short relative to the unstable period of the circuit, means are provided to prevent tube 11 from immediately returning to the conducting state except in the presence of a read out signal and yet be quickly susceptible to flip in'the presence of a read out signal.

This function is performed by diode 19 which is connected between `the grid of tube 11 and a source of voltage. The voltage source is slightly below the cutoff value for the tube 11 as established by the cathode bias created by conduction in the other tube, tube 12. This voltage source may be obtained through the use of a voltage divided placed between the plate supply voltage and ground. The divider is made up of resistances 2li and 21 with the cathode side of diode 19 connected tothe junction point 22 of the resistances. Thus, the grid of tube 11 is prevented from rising above the voltage of junction point 22 of the Voltage divider. Therefore, tube 11 will remain cut off until the positive bias on the cathode is reduced. This reduction in turn, will occur only when the conduction of tube 12 is limited. It should be understood that the diodes used in the circuit may be either crystal or vacuum diodes.

'For the circuit parameters shown in Figure l, tube 12 will not remain in state 1, i. e., the conducting condition, more than several hundred microseconds. The charge on condenser 17, created by the non-conducting conditions of tube 11, is dissipated through grid current and leakage across resistance 23. As a result of this decrease in grid potential in tube 12, conduction will cease in tube 12 after several hundred microseconds effecting an automatic reset or return to state 0. This reset is accomplished when the current drawn by tube 12 decreases to such an extent that the bias developed across cathode resistance 18 has decreased to a value whereby conduction in tube 11 commences again. As current flow in tube 11 increases, the `plate voltage falls. `This negatively going voltage coupled to the grid of tube 12 by condenser 1'7 tends to create a more negative charge on the grid of` tube 12. The potential of the grid after receiving this negative charge would 'tend to 'be less than ground potential. Di-'ode 24 is, therefore, connected between the grid of tube 12 and ground.' to prevent the grid from becomlngV biased below ground; the diode is `commonly known.. as a D. C." restorer. This restoring.V action is necessary since theamount ofbias below groundvwould tend. toincrease witheachcycl'e untiltu'be 12 could no longer be pulsed into conduction.v

It has been shown that the .circuit will automatically reset after a period of time. Normally thevinformation contained in the circuit, as ,represented by its state of conduction, will be readout byanother negative pulse. The readfout pulse is -applied .to terminal ZSUWhereby-,it is transmittedthroughl coupling. condenser ;26,diode 27 and condenser .17 to the grid oftube 12. If `tubev 1I?,` is cutoff atthe time the .read outpulse is applied, it has no eict on the conduction state of the circuit.. The pulse has little effect on. thevplate voltage'of-tube.11, and the driving more negative of thegridiof tube-,12 will have noy electif it is, read out pulse is applied to the circutin statef.0'v(tube 12 Vnot conducting), no signall-isreceived at outputterminals 28 which to the cathode of tube 12 through. coupling;condenserf30t However,. if `thejcircuit. is` in state 1 when the pulse is applied, therewill .be anxoutput produced aswell -as a` resettingfof the circuit tofstate 0. If tube 12 isilconducting when the negativev pulse charges condenser 17, Vthev` pulse vwill tend. toreduce the gridvoltage. The grid voltage :drop-will be accompanied by a'reduction. in cur-i rent flow throughtube 12,which will reducethefcathode bias.acrossvresistance18,y When the cathodebas drops slightly, tube 11, the grid of which was just slightlybelowcutol, `will begin to'conduct This conductionxde creasesthevoltage at the-plate of .tube 11; the negative goingvoltagevont the plate of tube 11, as was vexplained above,rcreatesaf more negative grid voltage in tube 12. This action continues until tube 12 is` and tube.11is conducting.4

The change in condition of tube 12 fromconductingito non-conducting will eiect a change in cathode. bias; Tube11 is limited in current conduction to a.value.less than tube 12 by resistance. 15. Thus vthe cathodefbias' willdecrease in changing from'state 1 to state 0.` This change in voltage will be transmitted throughicoupling condenser 30 to output` terminals 28. Thus, .whenf tube 12` is conductingrgat the time a read out pulse iisv received, a signal will beproducedatl the output terminal's`28.

Ifithe circuit is in state:Oawhenzthereadout pulse is" received, there will be no .changeinr circuit state:andno f output .pulse produced atterrninals 28.l

To eect the advantagespossible with-the circuit of Figure 1, appropriate.circuitzvaluesz-must be chosen -wit'n certainfactors inmind. For. exampleyto rnake'possibleV the :high .repetition rate desired or V.rapid recoveryy time 'of the circuit, the time constant of grid-'charging-circuit of tube'll should be-.made very: short.V This part of the circuit includes resistance.. 16, between the platesupply` and grid, and: condenser 14y whichbcouples-thefgrid of tube-11.1to the trigger source-of :binary-inforrnation.y Thepurpose of the-short time-constant is topermit theegrid on: cut'ol of tube 11-bya= negative pulse,V toret'urn quickly vtoa pointslightlyl below'cutol. This short'-'tir`neVV constant would result in -rapid 'returnofthe-circuit tofstate but -for the clamping-actionv ofthe-voltage divider andv diode 19 which prevent the grid vfromwrisin'g aboved cutoi. By returning the-grid 'cathode voltage-"oftube-A llrapidly'tol a value belowy cutoif, theJ tube 11 willbe" rapidly placed'in a condition) to` respond" to a slight? changein the cathode' bias as effected by 'areadout" pulse initiating conduction in tube 122 Because ofthe sensitive state of tube 11, avery small negative pulse is suicient to start' condctionintube,11,Vv which, `because of its decreasingplatovoltage, will .completerthe cutolfVV cutoff. Therefore` when, a

are connected across loadJresistor 29l completely cutolff.A

dividing resistances 20 and 21, the time constant of` resistance 16 and condenser 14 were made long enough to keep the grid of tube 11 below cutoff during the unstable state of the circuit, itwill be seen that tube 11 would have beenrelatively insensitive to `change except at the very end ofY the unstable period Vofz-the-y circuit'.` Because fof theY exponential. approach lto cutoi by the grid of tube 11 as produced by theftimeV constant: of resistance-16 and condenser 14, the grid would be biased far below cutoffV duringrthe early part of the unstable period thus requiring amuch larger pulse to cause it to conduct. By useeof'the;` divide'rgand".diode,i.thef.time constant may be very short without shortening the unstable period,;thuspermitting. the tube 11 .tobeabiasedtto a sensitive condition. during .the entire'unstablaperiod...

It shouldalso benotedtthat. the reset'function may ifbe accomplished i111V two ways. The. read.. out. pulse 'may automatically reset the circuit.to.;state- 0', 4or: in the:

absence .of anypulse,` therfcircuitwill' automatically return. ktostate. .0.'l The J speed..of i the latter v*reset Scan. be-

regulated .byr the'v valuesof. .condenseri 17. and Agrid..I leak resistor23 which areconnectedttoithegrid of tube 12'. The circuit of Figure 2 represents aLmorerened-ivers sion.: of the. embodimentof Figureiv 1 whichJ operates; in

substantially. the same manner.:r Ai; dilerent means` f isi shown for. obtaining anfoutput :pulse :when: archange-inn state has-been elfectedf. Inraddition, the bias .voltagesl on the circuit Vhave ibeen'changed fas shown.

The triodes r11 and 12iperform1a1fsimilar function in Figure 2 as finhFigurel indicatingthe states of'v the: circuit by conductioninf one of.- the twoAtubes.I The otherv Diode 32 'has been insertedf between thef gridY and cathode of tube 11 to prevent the grid voltage of1tube11-' from exceeding the-voltagefdeveloped 'across the cathode resistor durin'g the period of conduction in` tube 11.- By thus limitingftlie grid'voltage ine'stateA 0,1 the'circuitis sensitive' to'ismall'erin'putl trigger pulsesf` The circuit'u is 'alsopi'ovidedL withetwo-e means Iof 'taking' an outputin responseto a change-inconductionof tube 12. Output terminal 33 is connected to-th'efcommon'cathode con--V nection. A-s was poin'tedoutVA previously,y thereA will-"be diterent voltages across Acathode biasresistor118 depend-- ing on which of the two tubes is conducting.- Because ofA the lower' impedance in' theffcircuit offtub'e 12; it willdraw more :current and henceeproduce alarger'drop across resistance-1S? The-use-off'thehig'her plate'volt'age onl tube12 further increases the-rati'o'between`- thefvoltage in state 1 and state 0: It can befseen'Y therefore 'thatthemagnitudeof -the^voltage at terminal'33""vvouldl indicate the storage state of the circuit.- it should be -noted^`that both circuits areI welladapted to producelowimpedance outputs without the use of anextra cathode follwere circuit;v This feature, ofcourse; resultsiin tube economy inh many applications of this type of circuit.

If a' pulse outputisdesired, an -alternative to *themeans shown in-^Figure^1 is theetransformer'couplingto i the'plate circuit'of 'tube12 'as-shown'in Figure-2. Transform er 3.4"isconnectedA with'its primary, 35`-between the" plate `supplyvoltage and the-plate.' Output' terminals-` 37 are connectecltc')the'endsv of secondary winding 36:'

When tube 12"is` conducting, statel,v aV read outpulse;

whichwill "cutoi tube 12as explained above',v will 'cause a p ulseto beproduced at terminals 37. This pulseJre-' sults from .the cessation of 4current tlowingthrough'tube '12 and primary winding 35. Diode 38 is connected in parallel with coil 35 to damp out any oscillations developed in coil 35. It should be noted that the polarity of the diode is such that only the initial oscillation created on terminating the ilow of current in tube 12 will appear at the output, the succeeding oscillation being shorted out by the diode 38. When current begins flowing in tube 12, no output will be received since the initial oscillation is shorted out by the diode 38.

It should be understood that the characteristics of transformer 35 are chosen to give the desired sharpness or peaking of the output pulse.

Voltage divider 39 made up of resistances 40 and 41 is provided to negatively bias the grid of tube 12 well below cutoi during periods of conduction in tube 11. This negative bias becomes necessary to assure cutofl` of tube 12 when operating with a plate voltage substantially larger than tube 11. Thus, the divider 39 is connected between ground and the 150 volt negative source. The grid of tube 12 is then connected through grid leak resistance 23 to the junction point of resistors 40 and 41. Diode 24 serves as a D. C. restorer as in Figure l to prevent the grid from being biased below the potential of junction point of the divider.

Coil 42 has been added to the plate circuit of tube 11 to provide an RL peaking circuit which will speed the action of the circuit when tube 11 is cutoff.

Obviously many modications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

What is claimed is:

l. A digit storage circuit comprising rst and second electron tubes, the first of which is normally conducting; each of said tubes having at least a cathode, a control grid and a plate electrode; said tubes having a common cathode load impedance; output terminals connected across said cathode load impedance; a iirst time constant circuit connected to said rst tube grid; said iirst time constant circuit including a rst condenser for applying a negative read-in pulse representative of a binary indication to the grid of said first tube; a second time constant circuit; said second time constant circuit including a second condenser connected between said first tube plate and said second tube grid and a grid leak resistor connected to said second tube grid; a voltage source; means connecting said rst and second tubes to said source of voltage such that the maximum tube current in said first tube is less than the maximum tube current in said second tube; the means connecting said rst tube and said voltage source including a serially connected resistance-inductance peaking circuit; biasing means having a voltage output of a magnitude in the vicinity of and less than the cut-oil grid voltage of said rst tube when said second tube conducts, unidirectional means interconnecting said biasing means and said rst tube grid such that the Voltage on said iirst tube grid is limited to the magnitude of said biasing means output; said rst time constant circuit being adapted to control the time duration requisite to return said irst tube grid to the magnitude of said biasing means output following a negative read-in pulse to said rst tube grid; the time constant of said second time constant circuit being greater than the time constant of said rst time constant circuit; and read-out pulse means connected to said second tube grid and operative to stop conduction in said second tube, and to produce an output voltage indication, when said second tube is conducting.

2. A digit storage circuit comprising rst and second electron tubes, the rst of which is normally conducting; each of said tubes having at least a cathode, a control grid and a plate electrode; said tubes having a common cathode load impedance; output terminals connected across said cathode load impedance; a first time constant circuit connected to said first tube grid; said rst time constant circuit including a iirst condenser for applying a negative read-in pulse representative of a binary indication to the grid of said rst tube; a second time constant circuit; said second time constant circuit including a second condenser connected between said iirst tube plate and said second tube grid and a grid leak resistor connected to said second tube grid; a voltage source; means connecting said first and second tubes to said source of voltage such that the maximum tube current in said first tube is less than the maximum tube current in said second tube; biasing means having a voltage output of a magnitude in the vicinity of and less than the cut-oirr grid voltage of said first tube when said second tube conducts, unidirectional means interconnecting said biasing means and said first tube grid such that the voltage on said rst tube grid is limited to the magnitude of said biasing means output; said first time constant circuit being adapted to control the time duration requisite to return said rst tube grid to the magnitude of said biasing means output following a negative read-in pulse to said rst tube grid; the time constant of said second time constant circuit being greater ei than the time constant of said rst time constant circuit; and read-out pulse means connected via said second condenser to said second tube grid and operative to stop conduction in said second tube, and to produce an output voltage indication, when said second tube is conducting.

3. A digit storage circuit comprising first and second electron tubes, the iirst of which is normally conducting; each of said tubes having at least a cathode, a control grid and a plate electrode; said tubes having a common cathode load impedance; output terminals connected across said cathode load impedance; a iirst time constant circuit connected to said rst tube grid; said iirst time constant circuit including a iirst condenser for applying a negative read-in pulse representative of a binary indication to the grid of said rst tube; a second time constant circuit; said second time constant circuit including a second condenser connected between said first tube plate and said second tube grid and a grid leak resistor connected to said second tube grid; a voltage source; means connecting said rst and second tubes to said source of voltage such that the maximum tube current in said iirst tube is less than the maximum tube current in said second tube; biasing means having a voltage output of a magnitude in the vicinity of and less than the cut-oil grid voltage of said first tube when said second tube conducts, unidirectional means interconnecting said biasing means and said first tube grid such that the voltage on said first tube grid is limited to the magnitude of said biasing means output; said rst time constant circuit being adapted to control the time duration requisite to return said first tube grid to the magnitude of said biasing means output following a negative read-in pulse to said first tube grid; the time constant of said second time constant circuit being greater than the time constant of said rst time constant circuit; and read-out pulse means connected to said second tube grid and operative to stop conduction in said second tube, and to produce an output voltage indication, when said second tube is conducting.

References Cited in the tile of this patent UNITED STATES PATENTS 

